In conventional DRAM sense amplifiers, a so-called "Vd/2 (where Vd=power-source voltage)" pre-charging circuit consisting of reflected bit lines, which employs complementary metal-oxide-semiconductor (CMOS) sense amplifiers, from the viewpoint of densification, noise tolerance or low power characteristics, is widely used.
FIG. 1 shows the construction of the conventional "Vd/2" pre-charging circuit. Note that in the figure, column-selecting gates are omitted because they are unnecessary in explaining the "Vd/2" pre-charging circuit. CMOS sense amplifiers (N1, P1, N2, P2) connected to sense-amplifier nodes (BM, /BM) are disposed in the central portion of the "Vd/2" pre-charging circuit. The sense-amplifier nodes (BM, /BM) are connected to left and right bit lines (BLl, /BLl, BLr, /BLr) through n-channel MOS (NMOS) isolators (N3, N4, N5, N6). By these NMOS solators (N3, N4, N5, N6), the CMOS sense amplifiers (N1, P1, N2, P2) are isolated from left and right DRAM cell arrays connected to the bit lines (BLl, /BLl, BLr, /BLr).
The circuit of FIG. 1 has pre-charging circuits (N10, N11, N12, N13) for pre-charging the bit lines and equalizer circuits (N8, N9) for equalizing electric potentials on the bit lines, outside the NMOS isolators (N3, N4, N5, N6). Also, an NMOS set driver (N7) is connected as a common driver to the sources of the NMOSs (N1, N2) of the plurality of CMOS sense amplifiers. Similarly, a p-channel MOS (PMOS) set driver (P3) is connected as a common driver to the sources of the PMOSs (P1, P2) of the plurality of CMOS sense amplifiers. The NMOS set driver (N7) is connected to ground, while the PMOS set driver (P3) is connected to a constant-voltage source (Vd).
FIG. 2 shows a timing diagram of the circuit of FIG. 1. The operation of the conventional circuit of FIG. 1 will hereinafter be described with reference to FIGS. 1 and 2. Pre-charge signals (PRl, PRr) both hold a logic high level during pre-charging or non-selection. The NMOS transistors (N7 to N12) are all switched on (conduction), so that all the bit line pairs are pre-charged to Vd/2. Isolation-controlling signals (ISOl, IOSr) hold a logic high level. Therefore, the NMOS isolators (N3, N4, N5, N6) are all switched on (conduction), and at the same time, the sense amplifier nodes (BM, /BM) are also pre-charged. At this time, an n-channel set signal NSET is low and the NMOS set driver (N7) is in an OFF (non-conduction) state. A p-channel set signal PSET is high and the PMOS set driver (P3) is in an OFF (non-conduction) state.
Assuming the left side cell array of FIG. 1 has just been activated, the pre-charge signal (PRl) goes low. The NMOSs (N10, N11) of the left side pre-charge circuit is switched off and pre-charging of the left side bit line pair (BLl, /BLl) ends. At the same time, the isolation-controlling signal (IOSr) goes low. The NMOS isolators (N5, N6) are switched off and therefore the right side bit line pair (BLr, /BLr) is isolated from the CMOS sense amplifier. After data on a cell has appeared on the bit lines (BLl, /BLl), the n-channel set signal NSET is made high and the p-channel set signal PSET is made low. The NMOS set driver (N7) and the PMOS set driver (P3) are both conducted (ON) and the potential difference (cell data) between the bit line pair (BLl, /BLl) is amplified by the CMOS sense amplifier. After the bit line pair (BLl, /BLl) has reached voltage levels of ground (Gnd) and Vd, pre-charging operation is again performed and a sequence of operations ends. The operation of the right side cell array will be performed in the same as the left side cell array.
The conventional circuit of FIG. 1, however, has the disadvantage that the amplification of the high (Vd) side of the sense amplifier and the rewriting of high data to a cell take time from the circuit construction. That is, the circuit of FIG. 1 has the disadvantage that a long time is required until the bit line (BLl) reaches a voltage level of Vd during amplification of the sense amplifier, as shown in FIG. 2 (upper waveform). The reason is that since the bit line (BLl) is charged by the PMOS set driver (P3) disposed after a lot of sense amplifiers connected in parallel through the NMOS isolator (N3) and the PMOS (P1) of the sense amplifier, the current driving force for transistors (N3, P1, P3) connected in series is insufficient with respect to the total bit line load. The high-speed operation of the transistors (N3, P1, P3) cannot be ensured and therefore it takes a long time to supply current (power) from the Vd power source to the bit line (BLl).